Verilog always @ posedge with examples — 2021
Verilog always block (blocking and non-blocking assignments) is explained in detail with examples. Also generation of MUX and Decoders Verilog.
In any digital interview, Verilog questions will be asked. Simple questions to confusing and tricky questions will be asked by an interviewer. He will be interested in knowing whether you are very clear with basic concepts or not. Verilog is a hardware description language makes it necessary to be learned by an digital design aspirant.
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Questions on blocking and non-blocking assignments, Verilog tasks vs Verilog functions, and Verilog modelling questions based on synthesis are the key concept oriented one’s which are preferred to ask by interview panel.
Well, let us cover some of the important concepts in Verilog HDL.
Verilog always block and assignments
Some important points about always construct,
1. A Verilog always construct start at 0 time units and executes indefinitely or never stops unlike initial construct starts at 0 time unit and executes only once.
2. An example where always can be used is to generate clock of a particular time period indefinitely. i.e. if T time period required is 10 time units then
always
#5 clock = ~ clock;
3. It is possible to have more than one always blocks in a Verilog module and all of them starts at 0 time units and executes concurrently.
4. It is always a must to have reg variable at LHS and RHS can be net or reg inside a always construct.
Let us consider some of different scenarios and see how this always construct behaves,
Situation 1, what happens for the below Verilog code snippet?
always @ (posedge clock)
y = x;
always @ (posedge clock)
x = y;
Points to be observed are,
1. Two always blocks with a same positive edge event triggered clock is given.
2. Verilog blocking assignment is used in both cases of above scenario.
3. Trying to swap x and y.
Behavior would be, the above situation leads to Race Condition, since always blocks executes concurrently either of the above two expressions executes depending on the simulator.
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Situation 2, what happens for the below Verilog code snippet?
always @ (posedge clock)
y <= x;
always @ (posedge clock)
x <= y;
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