Key points on Cache memory in detail and hit ratio

VLSI Universe
2 min readJun 8, 2021

In the computer architecture or computer organization(COA), cache memory is a very fast memory, which make sure the data reach from the main memory to the CPU faster. We will discuss in detail Cache hit ratio and types of cache memories in OS and The role of cache memory between CPU and main memory in computer organization and architecture.

Read the complete story at VLSI Universe Cache Memory

Cache memory in detail and hit ratio

The cache memory is nothing but a buffer between CPU and RAM. Parameters like Cache hit, Cache miss, Miss rate, Miss Penalty, Cache block, Cache line and Cache tag, we will understand all of them to increase the cache performance.

We will discuss in detail the cache memory and its working, various types of cache memories, what is cache mapping in memories, and how does locality of reference helps cache memory to manage its high speed and speed.

Read the complete story at VLSI Universe Cache Memory

We all know there is a very big bridge gap between memory and the CPU. Typically in the current generation, the CPU is faster than the memory, especially comparing with the main memory(RAM). A solution is to have the speed of the main memory(RAM) equals the speed of the CPU so the there is no room for waiting for the CPU to access the data or instructions from the main memory. So there is a need for a method or scheme by which the CPU can take the data and instruction from the main memory in the fastest possible way. That purpose is filled in by a Cache Memory in the operating system which does it in a better way as expected.

Let us look into detail, what is a cache memory, how it works, and what are main issues with proper block diagrams.

Table of Contents

1. Cache Memory in detail
2. Cache Memory Performance(Cache Hit and Cache Miss)
3. Types of Cache Memories
4. Locality of reference in memory
5. Memory Architecture and Different Levels
6. Cache Memory Mapping in COA
6.1 Direct mapping in cache memory
6.2 Associative mapping in cache memory
6.3 N-way set associative mapping in cache memory
7. Conclusion

Read the complete story at VLSI Universe Cache Memory

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